1. Field of the Disclosure
The present invention relates generally semiconductor processing. More specifically, examples of the present invention are related to semiconductor processing of image sensor pixel cells having global shutters.
2. Background
For high-speed image sensors, a global shutter can be used to capture fast-moving objects. A global shutter typically enables all pixel cells in the image sensor to simultaneously capture the image. For slower moving objects, the more common rolling shutter is used. A rolling shutter normally captures the image in a sequence. For example, each row within a two-dimensional (“2D”) pixel cell array may be enabled sequentially, such that each pixel cell within a single row captures the image at the same time, but each row is enabled in a rolling sequence. As such, each row of pixel cells captures the image during a different image acquisition window. For slow moving objects the time differential between each row generates image distortion. For fast-moving objects, a rolling shutter causes a perceptible elongation distortion along the object's axis of movement.
To implement a global shutter, storage capacitors or storage transistors, which may also be referred to as storage gates herein, can be used to temporarily store the image charge acquired by each pixel cell in the array while it awaits readout from the pixel cell array. When a global shutter is used, a transfer transistor is typically used to transfer image charge from the photodiode to the storage transistor, and then an output transistor is used to transfer the stored image charge from the storage transistor to a readout node of the pixel cell.
Factors that affect performance in an image sensor pixel cell having a global shutter include shutter efficiency, dark current, white pixels and image lag. The spacing between the transfer, storage, and output transistor structures, may have a significant impact on these factors. One tradeoff faced by designers when designing pixel cells is that as the structures of neighboring transistors (e.g., the transfer, storage transistors, and output transistors) are overlapped to reduce lag, some of the electrons become trapped in the deep implant regions between the neighboring transistors that cause “pinched” channels, which prevent some of the electrons from flowing to the output floating diffusions during transfer.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.